 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| HY5V62CF 4 Banks x 512K x 32Bit Synchronous DRAM DESCRIPTION The Hynix HY5V62C is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V62C is organized as 4banks of 524,288x32. HY5V62C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a 2N rule.) FEATURES * * * * JEDEC standard 3.3V power supply All device pins are compatible with LVTTL interface 90Ball FBGA with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3 * * Internal four banks operation * Burst Read Single Write operation Programmable CAS Latency ; 2, 3 Clocks * * * Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst * ORDERING INFORMATION Part No. HY5V62CF-7 HY5V62CF-S Clock Frequency 143MHz Power Normal Organization 4Banks x 512Kbits x32 Interface LVTTL Package 90Ball FBGA 100MHz This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Nov. 01 HY5V62CF PIN CONFIGURATION 1 A D Q 26 D Q 24 VSS VDD D Q 23 D Q 21 2 3 4 5 6 7 8 9 B D Q 28 VDDQ VSSQ VDDQ VSSQ D Q 19 C VSSQ D Q 27 D Q 25 D Q 22 D Q 20 VDDQ D VSSQ D Q 29 D Q 30 D Q 17 D Q 18 VDDQ E VDDQ D Q 31 NC NC D Q 16 VSSQ F VSS DQM3 A3 A2 DQM2 VDD G A4 A5 A6 A 10 A0 A1 H A7 A8 NC Top View (11m m x13m m ) NC BA1 NC J C LK CKE A9 BA0 CS# RAS# K DQM1 NC NC CAS# W E# DQM0 L VDDQ DQ8 VSS VDD DQ7 VSSQ M VSSQ D Q 10 DQ9 DQ6 DQ5 VDDQ N VSSQ D Q 12 D Q 14 DQ1 DQ3 VDDQ P D Q 11 VDDQ VSSQ VDDQ VSSQ DQ4 R D Q 13 D Q 15 VSS VDD DQ0 DQ2 PIN DESCRIPTION PIN CLK CKE CS BA0, BA1 A0 ~ A10 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection RAS, CAS, WE DQM0~3 DQ0 ~ DQ31 VDD/VSS VDDQ/VSSQ NC Rev. 0.4/Nov. 01 3 HY5V62CF FUNCTIONAL BLOCK DIAGRAM 512Kbit x 4banks x 32 I/O Synchronous DRAM Self Refresh Logic & Timer Refresh Counter CLK Row Active 512Kx32 Bank 3 Row Pre Decoder 512Kx32 Bank 2 X decoder 512Kx32 Bank 1 X decoder 512Kx32 Bank 0 X decoder DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate CKE CS RAS CAS WE DQM0 DQM1 DQM2 DQM3 State Machine Column Active X decoder Memory Cell Array Column Pre Decoder Y decoder DQ30 DQ31 Bank Select Column Add Counter A0 A1 Address buffers A10 BA0 BA1 Address Register Burst Counter Mode Register CAS Latency Data Out Control Pipe Line Control Rev. 0.4/Nov. 01 4 HY5V62CF ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit C C Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature Time TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 10 V V mA W C Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA=0 to 70C) Parameter Symbol Min Typ. Max Unit Note Power Supply Voltage Input high voltage Input low voltage VDD, VDDQ VIH VIL 3.0 2.0 VSSQ - 0.3 3.3 3.0 0 3.6 VDDQ + 0.3 0.8 V V V 1,2 1,3 1,4 Note : 1.All voltages are referenced to VSS = 0V 2.VDD/VDDQ(min) is 3.15V for HY5V62CF-7/S 3.VIH (max) is acceptable 5.6V AC pulse width with 3ns of duration with no input clamp diodes 4.VIL (min) is acceptable -2.0V AC pulse width with 3ns of duration with no input clamp diodes AC OPERATING CONDITION (TA=0 to 70C, 3.0V VDD 3.6V, VSS=0V - Note1) Parameter Symbol Value Unit Note AC input high / low level voltage Input timing measurement reference level voltage Input rise / fall time Output timing measurement reference level Output load capacitance for access time measurement VIH / VIL Vtrip tR / tF Voutref CL 2.4/0.4 1.4 1 1.4 30 V V ns V pF 2 Note : 1.3.15V VDD 3.6V is applied for HY5V62CF-7/S 2.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF) For details, refer to AC/DC output load circuit Rev. 0.4/Nov. 01 5 HY5V62CF CAPACITANCE (TA=25C, f=1MHz, VDD=3.3V) Parameter Pin Symbol Min Max Unit Input capacitance CLK A0 ~ A10, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 CI1 CI2 CI/O 2.5 2.5 4 3.5 3.8 6.5 pF pF pF Data input / output capacitance DQ0 ~ DQ31 OUTPUT LOAD CIRCUIT Vtt=1.4V Vtt=1.4V RT=500 RT=50 Output 30pF Output Z0 = 50 30pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (DC operating conditions unless otherwise noted) Parameter Symbol Min. Max Unit Note Input leakage current Output leakage current Output high voltage Output low voltage ILI ILO VOH VOL -1 -1 2.4 - 1 1 0.4 uA uA V V 1 2 IOH = -2mA IOL = +2mA Note : 1.VIN = 0 to 3.6V, All other pins are not under test = 0V 2.DOUT is disabled, VOUT=0 to 3.6V Rev. 0.4/Nov. 01 6 HY5V62CF DC CHARACTERISTICS II (DC operating conditions unless otherwise noted) Speed Parameter Symbol Test Condition -7 -S Unit Note Operating Current IDD1 Burst Length=1, One bank active tRAS tRAS(min), tRP tRP(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable tCK tCK(min), tRAS tRAS(min), IOL=0mA All banks active tRRC tRRC(min), 2 banks active CKE 0.2V CL=3 CL=2 120 115 mA 1 Precharge Standby Current in power down mode IDD2P IDD2PS 2 mA 2 IDD2N Precharge Standby Current in non power down mode IDD2NS IDD3P IDD3PS 15 mA 10 3 mA 3 Active Standby Current in power down mode IDD3N Active Standby Current in non power down mode IDD3NS 40 mA 25 210 210 180 mA 160 190 mA mA 2 1 Burst Mode Operating Current Auto Refresh Current Self Refresh Current IDD4 IDD5 IDD6 2 Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS I Rev. 0.4/Nov. 01 7 HY5V62CF AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -7 Parameter Symbol Min Max Min Max -S Unit Note System clock cycle time Clock high pulse width Clock low pulse width CAS Latency = 3 CAS Latency = 2 tCK3 tCK2 tCHW tCLW 7 1000 10 2.5 2.5 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 6 - 10 1000 12 3 3 3 2 1 2 1 2 1 2 1 2 6 8 - ns ns ns ns ns 2 ns ns ns ns ns ns ns ns ns ns ns ns 3 1 1 1 1 1 1 1 1 1 1 CAS Latency = 3 Access time from clock CAS Latency = 2 Data-out hold time Data-Input setup time Data-Input hold time Address setup time Address hold time CKE setup time CKE hold time Command setup time Command hold time CLK to data output in low Z-time CLK to data output in high Z-time CAS Latency = 3 CAS Latency = 2 tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 5.4 tOHZ2 6 ns Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v 3.Data-out hold time to be measured under 30pF load condition, without Vt termination Rev. 0.4/Nov. 01 8 HY5V62CF AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) -7 Parameter Symbol Min Max Min Max -S Unit Note Operation RAS cycle time Auto Refresh RAS to CAS delay RAS active time RAS precharge time RAS to RAS bank active delay CAS to CAS delay Write command to data-in delay Data-in to precharge command Data-in to active command DQM to data-out Hi-Z DQM to data-in mask MRS to new command Precharge to data output Hi-Z Power down exit time Self refresh exit time Refresh Time CAS Latency = 3 CAS Latency = 2 tRC tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF 62 62 20 42 20 14 1 0 1 4 2 0 1 3 2 1 1 - 120K 64 70 70 20 50 20 20 1 0 1 3 2 0 1 3 2 1 1 - 120K 64 ns ns ns ns ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms 1 Note : 1. A new command can be given tRRC after self refresh exit Rev. 0.4/Nov. 01 9 HY5V62CF DEVICE OPERATING OPTION TABLE HY5V62CF-7 CAS Latency 143MHz(7ns) 133MHz(7.5ns) 100MHz(10ns) tRCD tRAS tRC tRP tAC tOH 3CLKs 3CLKs 2CLKs 3CLKs 3CLKs 2CLKs 6CLKs 6CLKs 5CLKs 9CLKs 9CLKs 7CLKs 3CLKs 3CLKs 2CLKs 5.4ns 5.4ns 6ns 2.7ns 2.7ns 3ns HY5V62CF-S CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) tRCD tRAS tRC tRP tAC tOH 2CLKs 2CLKs 2CLKs 2CLKs 2CLKs 2CLKs 5CLKs 5CLKs 4CLKs 7CLKs 7CLKs 6CLKs 2CLKs 2CLKs 2CLKs 6ns 6ns 6ns 3ns 3ns 3ns Rev. 0.4/Nov. 01 10 HY5V62CF COMMAND TRUTH TABLE Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/ AP BA Note Mode Register Set No Operation Bank Active Read H H H H X X L H L L X H L H L X H H L L X X X OP code X RA L CA H L V V H H H X X X X L L Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop DQM Auto Refresh Entry Self Refresh1 Exit H H H H L H L H L H Entry Precharge power down Exit L H L H Clock Suspend Entry Exit H L L L H V X V V X H X H X H X X H L L H H X H X H X X H X H X H X X L L H X L H X L L X L L X H H X X H L X V X X X L L H L X X X L H L L X CA V H H L X X X X V X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Dont care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation Rev. 0.4/Nov. 01 11 HY5V62CF PACKAGE INFORMATION Rev. 0.4/Nov. 01 12 |
Price & Availability of HY5V62CF-S
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |